Digital phase meter with compensating means for asymmetric waveform distortion

ABSTRACT

A phase-measuring instrument for waves of the same frequency is shown in basic form, in which a digital phase shift (or phase delay) reading is obtained and which may be precalibrated to read numerically in degrees or fractional parts of degrees or radians. A short, basic timing (clock) pulse is first generated every time interval To, and these are counted down also to form an enabling gate of very long duration compared to To. A coincidence circuit generates a phase delay gate equal in duration to the time between positive-going zero crossovers of two waveforms of the same frequency to be measured. This phase delay gate and the aforementioned basic timing pulses and enabling gates are supplied to the three inputs of a coincidence circuit which operate to pass said timing pulses in bursts equal in duration to said phase delay gates, only when all three of said coincidence circuit inputs are present. A counter then evaluates each of said bursts, providing said digital readout. In more sophisticated form, the device takes an average reading between positive-going edges for half of a measurement cycle and between negative-going edges for the other half measurement cycle. Also included as refinements are circuits for avoiding erroneous reading in cases of such severe wave distortion that the positive half wave of the first wave begins before, but ends after, the positive half wave of the second wave.

Unit States ate 1 [72] Inventors Jean Pignard y; Bernard Wintz,Cessenaz, France [21] Appl. No. 817,968

[22] Filed Apr. 21, 1969 [45] Patented May 18, 1971 [73] AssigneeInternational Standard Electric Corporation New York, N.Y.

[54] DIGITAL PHASE METER WITH COMPENSATING MEANS FOR ASYMMETRIC WAVEFORMDISTORTION 6 Claims, 9 Drawing Figs.

[52] US. Cl 324/830,

[51] Int. Cl G011 25/00,

G041 9/00, G04f 1 H06 [50] FieldofSearch ..324/83 (D), 68(C);328/133,134,155

[56] References Cited UNITED STATES PATENTS 3,209,254 9/1965 l-lassmann324/68(C)X Primary Examiner--Alfred E. Smith Attorneys-C. CornellRemsen, Jr., Walter J. Baum, Paul W. Hemminger, Percy P. Lantzy andThomas E. Kristofierson i 1 CT: A phase-measuring instrument for wavesof the same frequency is shown in basic form, in which a digital phaseshift (or phase delay) reading is obtained and which may beprecalibrated to read numerically in degrees or fractional parts ofdegrees or radians. A short, basic timing (clock) pulse is firstgenerated every time interval T and these are counted down also to forman enabling gate of very long duration compared to T, A coincidencecircuit generates a phase delay gate equal in duration to the timebetween positive-going zero crossovers of two waveforms of the samefrequency to be measured. This phase delay gate and the aforementionedbasic timing pulses and enabling gates are supplied to the three inputsof a coincidence circuit which operate to pass said timing pulses inbursts equal in duration to said phase delay gates, only when all threeof said coincidence circuit inputs are present. A counter then evaluateseach of said bursts, providing said digital readout.

In more sophisticated form, the device takes an average reading betweenpositive-going edges for half of a measurement cycle and betweennegative-going edges for the other half measurement cycle. Also includedas refinements are circuits for avoiding erroneous reading in cases ofsuch severe wave distortion that the positive half wave of the firstwave begins before, but ends after, the positive half wave of the secondwave.

60MB4e/5'0/v C/ZCU/T 5, /0 T/M/A/G sax/5454a C M AMP/F/EZ 9 5C 6&4654706 0 eA/Aew 2 5 4705/4545 4 6/476 '7 AMPe/mge l 66A/5547'06 5 i F 50 am a 4 AND i j mew/W .5" D/G/ML D/SP/W DIGITAL PHASE METER WllTlI-llCOENSATING I WANS FOR ASYMMETRIC WAVEFORM DIISTORTION CROSS-REFERENCE TORELATED APPLICATIONS This application is filed in accordance with theright of priority provisions of the International Convention for theProtection of Industrial Property and 35 USC. 119, the herein subjectmatter having been originally filed in France on Mar. I5, I968,Ser. No.PV 143,939.

BACKGROUND OF THE INVENTION 1. Field of the Invention The inventionrelates to electric wave phase shift measurement for accuratelydetermining the relative phase of two periodic waves of the samefrequency.

More particularly, the present invention relates to an improved devicefor deriving a digital reading of, phase shift, notwithstandingsubstantial distortion of waves to be measured.

2. Description of the Prior Art Electronic methods of phase comparisonhave long been available, earliest in analog form. After establishingphasemeasuring signals (at the positive-going zero crossover of eachwave, for example), it was only necessary to integrate against asuitable time. base for the interval between those signals to obtain ananalog. reading displayed on a galvanometer or similar device.

More recent trends have been toward the greater accuracy and flexibilityof digital instrumentation for phase as well as frequency measurement.

The present invention presents an improved instrumentation over thestraightforward prior-art devices wherein arbitrary counting points gaverise to errors in measurement whenever waves to be measured weredistorted.

SUMMARY OF THE INVENTION It is also to be noted that digital subsystemsare usually readily incorporated into larger digital systems. This wouldbe a particular advantage of the present invention since phasemeasurement is often a subsystem requirement in electronic equipment.

The present invention employs as the final component thereof, a knowntype of digital counter and display, for example, the type using Nixie"tubes for the visual display. Such a counter and display is usable forfrequency or other measurements and accordingly, subject to major systemrequirements, may be time shared with other functions.

The principle object of the present invention was the provision of phaseshift measuring equipment for waves of the same frequency. The frequencybands in which the device is capable of performing have substantially nolower limit but are limited to the state of the art in respect todigital logic circuitry and components. In order to exploit the inherentaccuracy of the system, digital timing (cloclt) pulses must have arelatively high repetition frequency compared to the frequency of thewaves to be phase measured. A practical maximum usable frequency for thepresent invention would lie in the approximate region of 3 percent ofthe highest clock pulse frequency achievable, provided the accuracyrequirements are not stringent.

The system of the present invention basically may be said to includestructure to effect the following functional steps:

I. Squaring of positive half-cycles of input waves to obtainwell-defined leading and trailing (positive-going and negative-going)waveform edges marking the respective zero crossovers of the waves to bemeasured.

2. Application to logic circuits to develop phase delay gates ofduration equal to the time between square wave positive-going edges.

3. Gating of the clock pulse during occurrence of said phase delay gatesto provide these pulses in bursts.

4. Counting of individual clock pulses in the aforementioned bursts overthe period of a. measuring gate (enable gate) several cycles (of inputwaves) in duration and presentation on a digital display.

Refinements in the structure of the invention disclosed includeaveraging between leading-edge time separation and trailingedge timeseparation to correct for wave distortion. An additional logic circuitrecognized erroneous reading due to distortion so drastic that theleading and trailing edges of a phase-shifted squared input wave do notnecessarily both follow the respective leading and trailing edges of afirst wave presumed to be in phase lead.

Another refinement concerns the introduction of an inhibit or data, notgood" signal from the register of the digital counter associated withthe display if the hundreds digit of the said register contains areading other than I Elaboration of the foregoing and other features andcapabilities of the invention are contained in or will be understoodfrom the Detailed Description" following.

BRIEF DESCRIPTION OF THE DRAWINGS For purposes of illustration anddescription, drawings are presented as follows:

FIG. 1 is a simplified block diagram of a digital phasemeter accordingto the invention;

FIG. 2 illustrates the wave shapes representing the signals observed atvarious points within the circuits of FIG. 1;

FIG. 3 depicts wave shapes explaining the effect of wave distortion onthe phase measurements;

FIG. 4 shows a block diagram of an alternative of the above phasemeterin which the effects of the distortion shown in FIG. 3 are compensated;

FIG. 5 illustrates the wave shapes representing the signals observed atvarious points in the circuits of FIG. 4;

' FIG. 6 illustrates the wave shapes in a mode of operation of thedevice of FIG. 4 resulting from exaggerated distortion of the second ofthe waves to be compared in phase;

FIG. 7 shows an additional circuit for use with the circuits of FIG. 4to prevent erroneous reading under exaggerated distortion conditions;

FIG. 8 wave shapes show a second example of operation of the circuit ofFIG. 7; and

FIG. 9 wave shapes show a second example of operation of the circuit ofFIG. 7.

DETAILED DESCRIPTION Referring now to FIG. 1, the basic components ofthe digital phase meter will be found.

A pulse generator I provides the basic (positive) timing or clock pulsesse of period T T would normally be a very small fraction of the periodof the waves to be measured, and the pulses themselves may be as shortin duration as l microsecond or less, consistent with digital computertechnology. Another pulse generator 2 is directly synchronized via itsinput lead 9 with pulse generator I and generates an enabling gate sm,the duration of which is k times the period of the timing pulses, thatis, k T,,. A comparison circuit 3 receives on its inputs A and B the twowaves (the phase dilference of which is to be measured) and supplies foreach incoming wave period, a periodic phase delay gate sp. This signalsp begins when one of the incoming waves passes through zero inthepositive direction and ends when the other passes through zero in thesame direction. The more detailed description of comparison circuit 3 tofollow will point out how this-is accomplished. Acoincidence or ANDcircuit 4 receives on its three inputs which are the phase delay gatesp, the continuous timing pulses sc, and the enable gate sm. When thesethree signals coincide (i.e., are present at any one time), an outputsignal S is passed by AND gate 4. Finally, a digital display counter 5receives the S signals originated from 4. This device 5 includes acounter 6 which counts the impulses delivered on signal lead S. Aregister 7 which records the counter position at the end of each measureand a display 8 which displays the result in digital form through meanssuch as the well-known Nixie" tubes, or some other visual highspeedreadout.

The wave shapes of FIG. 2 illustrate an example of operation of thephasemeter according to the invention. These wave shapes represent thesignals observed at various points in the phasemeter circuits. In ageneral way for simplification purposes, the signal to be measured andwhich is applied at point A will be called signal A. Similarly signal Bis identified with input B of comparison circuit 3.

The operation of the phasemeter in FIG. 1 will now be described bysimultaneously referring to the waveforms in FIG. 2. The generator 1continuously provides timing pulses sc. The generator 2 supplies theenable gate signal sm asynchronously with respect to the waves A and B(the phase difference of which is to be measured). These A and B signalswill be assumed for the present to be two sinusoidal waves. When thewave A passes through zero (ground) potential in the positive direction,the comparison circuit 3 begins to supply a phase delay gate sp. Whenthe wave B further passes through the zero potential in the samedirection, the circuit 3 stops supplying the sp signal. Thus, theobtained sp signal has a duration 6 corresponding to the time shiftbetween both waves and indicated typically on FIG. 2. This processrecurs at each period of the two incoming waves.

The signals sp are supplied to the left input of the AND gate 4; andduring each signal sp if the enable gate signal sm is supplied to theright input of the AND gate 4, the latter becomes conducting. So long asthis condition is extant, timing pulses so, which are supplied by thegenerator 1 to the middle input of AND gate 4, are delivered as on leadS. [See FIG. 2 (S line).] There will be seen to be as many such impulsetrains are supplied for each enable gate as there are sp signals in theenable gate interval. I

If the period of waves A and B is T, the total number of output impulsesS (to be called X) is as follows:

It will be noted that the phase difference (expressed in degrees)between these two A and B waves whose period is T and which are timeshifted by 0 is equal to 360 BIT. It can be seen that, if k=360, thenumber of impulses (X) directly represent the phase difference indegrees.

Similarly, the phase difference could be obtained in scales, giving k anarbitrary value, such as in radians or fractions thereof. Obviously, thehigher the number k, the more precise is the measurement. Phase couldreadily be measured in thousandths of a degree if k is given the value360,000.

The impulses S representing the phase shift between waves A and B aresent to the counter 6 of the display counter 5 which counts them. At theend of each measurement, the content of counter 6 is sent to register 7.The latter controls the display 8 in digital form while the counter 6 isrestored to its 0" position for a new measurement. These techniques ofdigital counting and display are, of themselves, well known.

Concerning the details of generation of the phase delay gates sp,discussion of the components within, and operation of, comparisoncircuit 3 will be undertaken.

Within circuit 3, signals A and B will be seen to be applied to theinputs of amplifiers l0 and 11, respectively. These saturating orlimiting amplifiers produce outputs A1 and B1 which are square waves asshown in FIG. 2. The said square waves have constant predeterminedamplitude, and their durations are substantially the same as thepositive half waves of signals A and B.

Two NAND gates 12 and 13 receive the Al and B1 square waves respectivelyand operate to provide the b signals at their paralleled outputs. Themanner in which the bistable (scale of two) circuit 14 responds to theNAND gate outputs will be described.

By way of definitional clarification, the NAND gates are said to delivera zero output potential (ground) at low output impedance when its inputsare at a positive potential.

If at least one of the inputs is not positive, the NAND gate delivers apositive potential acting as a high-impedance source. The outputs ofgates 12 and 13 are connected together; therefore, the conductor b willbe positive if both gates deliver positive signals. On the other hand,if either of the gates delivers zero potential (at low impedance), itwill mask the positive output (high impedance) of the other; and theconductor b will be substantially at zero or ground potential.

The bistable circuit 14 has two inputs b and f and two outputs. Oneoutput is on the side 0" which controls the conductor a and, inparallel, one input of the gate 12. The other output on the side lcontrols the output conductor sp and one input of the gate 13. When thebistable circuit 14 is in position 0," its output on the side 0" ispositive whereas its output the side I is ground. These potentials areinterchanged when the bistable circuit 14 is in position l If it isassumed that it is initially in position 0, a positive impulse on itsinput b triggers it into position l The triggering occurs at the end ofthe impulse on its negative or declining edge. A new positive impulse oninput b restores it into position 0" in the same way. The input f servesto restore or lock the bistable circuit 14 into position 0. When f is ata positive potential, the bistable circuit 14 can respond to the signalsreceived on its input b. This positive condition at f is of relativelylong duration and corresponds at least to the enable gate duration sm.

Before a measurement, the signal (ground) applied to the input f holdsthe bistable circuit 14 in position 0. Consequently, the bistablecircuit 14 delivers a positive potential on the conductor 15 towards thegate 12. At the beginning of the measurement, the signal blocking thebistable circuit 14 through its input f is removed by independentcontrol means (not represented). It has been assumed for simplificationpurposes that the square waves AI and B1 are equal to zero at thisinstant. When a positive edge of the wave Al occurs, a positivepotential is supplied to the lower input of the gate 12. The latteroperates and delivers a zero potential output signal. The conductor band the input of the bistable circuit 14 pass from a positive potentialto a zero potential. This entails the triggering of the bistable circuit14 into position l The signal on the conductor 15 then takes a zerovalue, and the gate 12 becomes nonconducting and delivers a positivepotential through its output causing the signal on the conductor b tobecome positive. This cycle of internal events within circuit 3 explainsthe shape of the b waveform, particularly at 16 on FIG. 2. The bistablecircuit 14 also supplies a positive potential through its output l andthe comparison circuit 3 sends a phase delay gate sp to the left inputof the AND gate 4.

The signal sp is applied to the lower input of the gate 13. When apositive (rising) edge of the wave B1 occurs, the gate 13 operates andsupplies a zero potential output. The signal on the conductor b passesfrom a positive potential to a zero potential and controls the triggerof the bistable circuit 14 into position 0." The latter sends a zeropotential signal through its output 1, thereby interrupting the phasesignal sp.

The gate 13 is disabled, but as the signal on the conductor 15 becomespositive, the gate 12 operates and supplies a zero potential signal onthe conductor b. When the negative edge of the wave Al occurs, the gate12 disables, both gates 12 and 13 deliver positive potentials; and thusthe signal on the conductor b becomes positive. The circuit 3 is thenagain in its initial state.

The above-described operation is repeated for each period of the waves Aand B. Thus, the circuit 3 supplied a series of positive signals sp tothe g2 :t. 4, which also receives the positive-counting impulses 50 andthe enable gate sm. The gate 4 delivers a positive output potential inthe initial quiescent condition. During each signal sp in the course ofa given measuring interval defined by sm, gate 4' provides a potentialoutput S during each positive sc pulse. At the end of the measuringinterval, the signal sm becomes zero and the gate 4 disables.Simultaneously,the external disable signal f may appear anew and blocksthe bistable 14 in its 0" position.

From an understanding of these events, the manner of generating the spwaveform between rising edges (positivegoing zero crossovers) of A and Bwill be understood.

Referring now to FIG. 3, the effect on phase shift measurement ofdistortion of one (or both) of the waves A and B will be discussed. Inthe example of FIG. 3, the wave A is sinusoidal while the wave C isdistorted but hasthe same frequency. The distortion is such that itsteepens the positivegoing crossover and tends to flatten thenegative-going zero crossover. A corresponding, undistorted sinusoidalwave is represented by a dotted line (on the C waveform line) forreference. After passing through limiting amplifiers l0 and 11, squarewaves Al and C1 are obtained. The positive edges of the wave Cl will beseen to be delayed by an increment x. The negative edges, however, areadvanced by x. Therefore, the phase difference 01 cannot be measuredwith respect to the positive edges of the waves Al and Cl would belengthened by x and would have a duration of 0+x. If the phasedifference were to be measured from the negative edges, the phase delay'gate would be shorted by x, giving Gl-nr.

In view of the foregoing, the present invention provides a solutionconsisting of measuring the phase difference by producing phase signalsfrom the positive edges (duration 01+x during the first half of ameasuring interval, and from the negative edges (duration Ol-x) duringthe other half of the measuring interval. The lengthening of the former,thus, will be compensated by the shortening of the latter, and themeasurement will be relatively unaffected by the distortion. While thereis no guarantee that a distorted wave would be advanced by x on the onezero crossover and delayed by the same amount on the other zerocrossover, the usual distortion encountered in wave transmission isharmonic; and, therefore, the assumption is justified under thesecircumstances.

Referring now to H6. 4, description of the additional instrumentationrequired to accomplish this unique approach in accordance with thepresent invention, there can be found in the phasemeter of HO. 4, allthe components of that of FIG. 1, bearing the same references and havingthe same functions. However, the comparison circuit 3a is moresophisticated because an additional bistable circuit 17 and its controlcircuits (inverters 18 and 19, gates 20 and 25, and capacitor 21) havebeen added.

To the comparison circuit 3a, there has been added two switchable paths,between the common output of the gates 12 and 13 (conductor b) and thetriggering input of the bistable l4 (conductor 3). This comprises adirect transmission path including an inverter 22, a gate 23, and areversing transmission path including only the gate 24.

The inverter 22 is a single input gate of the NAND type. When fed a zeroor ground potential, it delivers a positive signal and vice verse. ifthe bistable 17 is in position 0, the gate 23 is conducting. This meansthat if the inverter 22 sends a zero potential to it, the gate 23delivers a positive output voltage and vice versa. The direct path thusintroduces two inversions which cancel out, as if the gates 12 and 13directly controlled the bistable M.

It is to be noted that at the same instant, the gate 24 of the inversepath, controlled by the other l output of the bistable 17, is disabled.Therefore, it delivers a positive potential (at high source impedance)which has no effect upon the lowimpedance signals supplied by the gate23.

Consequently, when the bistable 17 is in position 0," the operation ofthe comparison circuit 3a is exactly the same as that of circuit 3 inFIG. 11, i.e., it delivers on its outputsp the phase delay gatingsignals obtained between the positive edges of the input waves.

When the bistable 17 is inposition l the gate 23 is disabled while thegate 24 is conducting. Thus, gate 24 passes the signals originated fromthe gates 12 and 13 to the input of the bistable 14 after inverting themin the process. Therefore, the

- bistable M will be seen to trigger from position 0 to position 1" whenthe wave A1 passes from the positive level to the zero (ground) level(negative-going edge). It is subsequently restored into position 0 by anegative-going edge of the wave Cl. Consequently, when the bistable 17is in position 1, the comparison circuit 3a delivers phase delay gatesignals obtained from the negative edges of the incoming waves. It isthis particular switching which is the instrument of changing fromleading to trailing edge phase measurement as aforementioned.

The description may now proceed to the control circuits of the bistable17, that is, the circuits which switch the bistable 17 into position "0during the first half of a measuring interval in order that the phasedelay gate signals be obtained from the positive edges of the incomingwaves, and into position 1 during the second half of the measuringinterval, in order that the phase delay gate signals be obtained fromthe negative edges of the incoming waves.

To this end, the generator 2 also supplies a positive signal snbeginning at the middle of each measuring interval and continuing to theend of sm, as an additional separate output. This signal sn is sent toone input of the gate 25 and tends to render it conducting.

The other input of the gate 25 is controlled by a circuit which includesthe inverters 18 and 1'9, the gate 20, and the capacitor 21. lf thepositive Al wave is present, the inverter 18 feeds a zero potential tothe gate 20, which renders it nonconducting. The latter then delivers apositive potential which charges the capacitor 21 and renders the gate25 conducting. If the wave Cl is present (positive), the gate 25 isequally well enabled by the inverter 19 and the gate 20.

Thus, it will be seen that if either of the waves Al or C1 (or both) ispositive, the gate 25 operates as soon as the generator 2 supplies thesignal sn. Gate 25 also controls triggering of the bistable 17 inposition 1" in the middle of the measuring interval, which then switchesthe bistable control circuit 14 from the direct path onto the inversepath as. previously explained.

At any time when both input waves are equal to zero, this switching doesnot occur immediately. As soon as one wave becomes positive, the gate 20is disabled, causing the capacitor 21 to be charged. During thecapacitor charging time, the comparison circuit operates in response toa positive edge just appearing (triggering bistable l4) and stabilizes.When the capacitor 21 is charged to a predetermined potential, the gate25 operates and triggers the bistable 17 into position 1"; and at thattime, the aforementioned switching takes place.

Therefore, the object of the above-mentioned circuit (inverters 18 and19, gate 20, and the capacitor 21) is to delay the switching from thedirect path onto the inverse path, as long as the waves Al and C 1 equalzero. A careful analysis of the comparison circuit operation conditionsreveals that otherwise a transitory anomaly in the phase delay gategeneration would occur, but is avoided by addition of the abovedescribedadditional logic circuitry.

A review of the operation of FIG. 4 with reference to the wave shapes ofFIG. 5 will help to understand the variation of the sp signal durationand the difference in the b waveform between halves of the measuringcycle as marked by the illustrated bistable 17 cycle. At the outset of ameasuring interval, the signal f is cancelled as aforementioned; and thesignal sm is extant. The square waves Al and C 1 obtained from the wavesA and C equal zero, and bistables l4 and 17 are in position 50.11

The gate 24 is nonconducting while the gate 23 is conducting. Asabove-mentioned, the direct path" is open; and signals from theconductor b pass to the conductor 3. The comparison circuit operation isidentical at this time to that of FIG. 1, in that it delivers sp signalsgenerated from the positive edges of the'waves Al and C1 as amplydescribed hereinbefore. It will be noted accordingly that b and gwaveforms on FIG. 5 are identical for this first half measuring cycle.

After half of the measuring interval has elapsed, the generator 2,through its signal sn triggers the bistable 17 into position l The gate24 is rendered conducting, while the gate 23 is blocked. The inversepath is thus opened instead of the direct one, and the signals from theconductor b are passed after inverting conductor g. I

It has been assumed that the triggering of the bistable 17 occurredwhile the wave Al was positive, and the bistable l4 in position Ireceived a positive potential on the conductor g. The changing of thepath reverses the latter signal, causing it to become equal to zero andthereby to trigger the bistable 14 into position 0. Consequently, thegate 23 operates and delivers a ground output potential. Similarly, gate24 provides a positive potential on the conductor 3. The bistable 14then remains in position Later on, at the arrival of a negative-goingedge of the wave Al, the gate 12 will deliver a positive potential andthe gate 24 to a zero potential, triggering bistable 14 into position 1"(beginning of the first phase delay gate signal sp since the switchingoperation). At the time of the next negative edge of the wave C1, thegate 13 will deliver a positive potential, which causes bistable M totrigger into position (end of the phase signal .rp). The introduction ofan inverse path between the conductors b and 3 thus enables the phasedelay gate signal generation from the negative edges of the waves to bemeasured instead of obtaining them from the positive edges. It will benoted that the illustrated sp signals in FIG. 5 are correspondinglyshorter in duration than those of the first half measuring cycle.

Various other operation examples may be contemplated when the signal snappears (switches) depending upon the incoming waves and position ofbistable 14. All result in the replacement of the phase delay gatesignal generation from the positive-going edges of the incoming waves tothe negative-going edges of the same waves.

It is to be noted that in the ultimate, the circuit of FIG. 4 does notsufiice by itself in all possible combinations of input .waves for thephase measurement. Indeed, when the distortion advances thenegative-going edges of the wave Cl more than the actual -phasedifference to be measured delays, then the phase signals sp generatedfrom these negative edges are erroneous, as it will appear by referringto FIG. 6.

FIG. 6 represents the wave Al, which is the same as in theaforementioned examples of operation, and a wave C2 having the sameshape as the wave CI of FIG. 3, but slightly delayed by 02 with respectto Al. The distortion always advances the negative edges by the durationsc; but it can be seen that 92 is shorter than x; and a negative-goingedge of C2 occurs before the corresponding negative edge of Al, whereasit should occur later as is the case for the positive edges. FIG. 6 alsorepresents the signals sp generated, in this case, by the cirggts ofFIG. 4 during'the first half of the measuring interval (K2) and duringthe second half K2).

The signals sp are normally and correctly obtained from the positiveedges during the first half of the measuring interval; however, thesignals sp further generated from the negative edges are erroneous asalready indicated. Whereas they should have'a duration equal to 02-x,their actual length is T+62. There in arises an error of T (a period ofthe waves to be measured) during this half of the measuring interval,resulting in a net display error of T/2 or 180.

What has just been described also applies to the situation when thedistortion direction is reversed and a negative-going edge of the waveCl, which normally should preceded the corresponding negative-going edgeof the wave A1, occurs after it due to the distortion.

The present invention thus also concerns an error detection circuitallowing the detection of such an error and providing for itscorrection. The circuit providing this additional function isillustrated in FIG. 7, and its operation will be described by means ofthe 'wave shapes of FIGS. 8 and 9.

The additional circuitry includes an error detection device which isillustrated in FIG. 7 and mainly comprises two input gates 26 and 27,two bistables 32 and 33, an output gate 36, and two capacitors 34 and 35within 39, the error detector. A dotted line encloses the newly addedcircuitry 39, separating it from the existing circuits from FIG. 4. Theinverters 18 and 19 are shown for reference on FIG. 7; Thus, will be eenthat the inputs of the FIG. 7 device are A1, C2, A1, and C1, as well asother control functions to be described.

The gate 26 (of the NAND type) is controlled by the wave A1 and bythegnverted wave C2, from the inverter 19 and referred to as C2. If atany moment of the measurement, the wave A1 is positive while the wave C2equals zero, the gate 26 operates and delivers a zero or groundpotential towards the bistable 32.

The bistable 32 consists of two gates (of the NAND type) 28 and 29.Before any measurement, the aforementioned signal f equals zero anddisables the gate 29, the latter delivering a positive potential to thegate 28. If the gate 26 is also nonconducting and therefore delivers apositive output potential, the gate 28 operates and sends a zero(ground) which disables the gate 29. The bistable constituted by thegates 28 and 29 is then said to be in position O." At the beginning of ameasurement, the signal f becomes positive. Whenever the gate 26delivers a zero signal, the gate 28 becomes nonconducting and delivers apositive potential. ln response, the gate 29 operates and delivers azero (ground) which disables the gate 28, even if the output ofthe gate26 becomes positive anew. The bistable will have triggered to position land will remain in this state until the signal f re stores it toposition 0." Thus, it records the coincidence Al/C2.

The gate 27 is similarly controlled by the wave C2 and by the in lgrtedwave Al supplied by the inverter 18 and referred to as Al. This gatecontrols a bistable 33 consisting of gates 30 and 31. These three gatesas their arrangement and operation are identical to those abovedescribed (gates 2 28, and 29). The bistable 33 thus records thecoincidence Al/C2.

The gate 36 is a NAND-type gate controlled by the bistables 32 and 33and by a signal on lead 38 delivered after the end of a measurement.

Before describing the functions of the other FIG. 7 components indetail, the overall operation of the error detection circuit of FIG. 7will be related to FIGS. 8 and 9.

The wave shapes of FIG. 8 illustrate the case when the distortionlengthens the positive alternations of the wave C2 so much that anegative edge of this wave (which should normally be fore thecorresponding negative edge of the wave Al in the same manner as for thecorresponding positive edge) is delayed so that it actually appearslater rather than before. It can be seen immediately that, in this case,when the wave A1 is pos i t ive, the wave C2 is also positive.Consequently, the Al and C2 conditions never obtain; and accordingly,the bistable 32 remains in position 0" and delivers a ground potentialon the conductor j, thus blocking the gate 36.

The wave shapes of FIG. 9 illustrate the case when the distortionshortens the positive alternations of the wave C2 so that a negativeedge of this wave, which should normally occur after the correspondingnegative edge of the wave A1 (as is the case for the positive edge), isadvanced so that it appears earlier. It can be seen immediately that, inthis case, when the wave C2 is positive, the wave Al is also positive;and consequently, the A1/C2 conditions never obtain. Therefore, the gate27 does not operate, and the bistable 33 remains in position 0" anddelivers a ground potential on the conductor h, thus disabling the gate36.

It will not be noted that in both cases when the distortion causes ashift of the negative edge of the wave C2 leading to a measurementerror, the gate 36 remains disabled. After the end of the measurement,the signal cor on lead 38 has no effect. The gate 36 sends a pisitivesignal through its output wire M, which indicates that the measurementcarried out is shifted by a half period. This signal can be used tolight a lamp which calls attention to the display error, or toautomatically correct the display by, for example, modifying the contentof the counter 6 by subtracting 180. The signal on lead 38 may bethought of as a data good inquiry control which may be manually operatedor automatically supplied at the end of a measurement cycle. It is anecessary but not sufficient signal to operate gate 36 to obtain asignal on output M if otherwise warranted.

In all other cases, the two bistables 32 and 33 both operate and deliverpositive signals towards the gate 36. At the end of the measurement,when the signal on lead 38 is supplied, the gate 36 operates anddelivers a ground potential through its output wire M which indicatesthat the measure is correct.

The capacitors 34 and 35 operate to cause a measurement to be consideredas erroneous and a corresponding false reading i ndicat ign given whenthe duration of the coincidences Al/C2 or Al/C2 is short, that is, whenthe positive or negative edges of the two waves to be measured are closeto one another. It is difficult to predict signal propagation times andcircuit operation times with sufficient accuracy and repeatability.Consequently, it is necessary to consider the case when the negativeedges of both waves are very close in time as indeterminate.Irrespective of the real order of these close edges, the phase meteroperates as if it were in the Al/C2 order (coincidence for this purposeconcerns the capacitors 34 and 35.

The capacitor 34 is connected between ground and the output of the gate28. When the bistabl e 32 is position 0, this capacitor is not charged.If the Al/C2 conditions are met, the gate 26 operates and disables thegate 28. The latter tends to deliver a positive signal and to triggerthe bistable; however, this positive signal must first charge thecapacitor 34 before the gate 29 may operate and the bistable 32 triggerto the 1 position. lf the duration of the coincidence A1/C2 is short,the capacitor 34 will not have had time to be sufficiently charged.While the gate 26 disables, the gate 28 operates anew, since the gate 29has not operated, and the bistable 32 remains in position Thus, thecapacitor 34 enalllgs the bistable 32 not to respond to the coincidencesA1/C2, when they are short. The capaci tgr 35 has the same function withrespect to the coincidence Al/CZ and the corresponding bistable, etc.

This gate 37, as illustrated in FIG. 7, is controlled by the signal corat the end of the measurement and by a signal dc originated from theregister 7 of the display device 5. The signal do is supplied by theregister 7 when the hundreds digit of the indication to be displayed indegrees is different from 1. The gate 37 always operates at the end ofthe measurement when the hundreds digit of the number to be displayed isdifferent from I. It delivers a ground potential at low impedance whichswamps any positive potential supplied by the gate 36, thereby effectingdisregard of the error detection output M.

Inhibition of this correction error indicator signal is desirable sinceit is not significant when the measurable phase difference is far fromthe areas of possible ambiguity above discussed.

It will be noted that the device of the present invention is readilyinstrumented with solid-state components and techniques, however, itsscope is not limited to the specific details of circuitry.

A1/C2). The manner of effecting the lock We claim:

1. A digital phase meter for measuring phase difference between firstand second periodic input waves of the same frequency, comprising:

comparison means responsive to said first and second input waves forgenerating a phase delay gate for each cycle of said waves, equal induration to the difference in time between a predetermined point on saidfirst wave and a corresponding point on said second wave;

means for generating a continuous series of timing pulses of repetitionfrequency large compared to the frequency of said waves to be measured;

an enabling gate generator interconnected with said means for generatingtiming pulses for producing enable gating pulses relatively long induration and equal to a predetermined integral number of pulserepetition intervals of said timing pulses, and further equal induration to at least one cycle of said first and second waves;

pulse control responsive to said timing pulses, said enable gate pulsesand said phase delay gates for passing said timing pulses in burstduring such time as said timing pulses, enable gate pulses, and phasedelay gates are all extant at said pulses control means; and

digital counting means for counting pulses within said bursts duringeach enable gate, thereby to provide a digital number indicative of thephase shift of said second input wave with respect to said first inputwave.

2. The invention set forth in claim 1, wherein said predetermined pointson said first and second input waves are defined as their positive-goingzero crossover points.

3. The invention set forth in claim 2, further defined in that saidenable gate generator includes means to generate a switching signalwhich is in a first switching condition substantially during the firsthalf of said enable gating pulses and which is in a second switchingcondition substantially during the second half of said enable gatingpulses, and said comparison circuit includes means responsive to saidswitching signals for enabling the generation of said phase delay gatesfrom said first and second input wave positive-going zero crossoverpoints during said first switching condition, and between theirrespective negative-going zero crossover points during said secondswitching condition.

4. The invention set forth in claim 3 further defined in that saidcomparison means includes means for converting said first and secondinput waves into corresponding first and second auxiliary waves ofstandarized amplitude and duration, each equal to the positive halfcycle of the corresponding input wave.

5. The invention se forth in claim 3 further defined in that saidcomparison means also includes an error detection circuit for providingan indication of erroneous reading comprising logic circuit means fordetermining whether or not the first occurring positive-going edge, andif not to disable the output of said comparison means.

6. The invention set forth in claim 5 further defined in that saiddigital counting means includes means for generating a disabling signalwhen the register of said counting means registers other than 1 in itshundreds digit, and further means are included for applying saidregister disabling signal to the output of said error detector.

1. A digital phase meter for measuring phase difference between firstand second periodic input waves of the same frequency, comprising:comparison means responsive to said first and second input waves forgenerating a phase delay gate for each cycle of said waves, equal induration to the difference in time between a predetermined point on saidfirst wave and a corresponding point on said second wave; means forgenerating a continuous series of timing pulses of repetition frequencylarge compared to the frequency of said waves to be measured; anenabling gate generator interconnected with said means for generatingtiming pulses for producing enable gating pulses relatively long induration and equal to a predetermined integral number of pulserepetition intervals of said timing pulses, and further equal induration to at least one cycle of said first and second waves; pulsecontrol responsive to said timing pulses, said enable gate pulses andsaid phase delay gates for passing said timing pulses in burst duringsuch time as said timing pulses, enable gate pulses, and phase delaygates are all extant at said pulses control means; and digital countingmeans for counting pulses within said bursts during each enable gate,thereby to provide a digital number indicative of the phase shift ofsaid second input wave with respect to said first input wave.
 2. Theinvention set forth in claim 1, wherein said predetermined points onsaid first and second input waves are defined as their positive-goingzero crossover points.
 3. The invention set forth in claim 2, furtherdefined in that said enable gate generator includes means to generate aswitching signal which is in a first switching condition substantiallyduring the first half of said enable gating pulses and which is in asecond switching condition substantially during the second half of saidenable gating pulses, and said comparison circuit includes meansresponsive to said switching signals for enabling the generation of saidphase delay gates from said first and second input wave positive-goingzero crossover points during said first switching condition, and betweentheir respective negative-going zero crossover points during said secondswitching condition.
 4. The invention set forth in claim 3 furtherdefined in that said comparison means includes means for converting saidfirst and second input waves into corresponding first and secondauxiliary waves of standarized amplitude and duration, each equal to thepositive half cycle of the corresponding input wave.
 5. The invention seforth in claim 3 further defined in that said comparison means alsoincludes an error detection circuit for providing an indication oferroneous reading comprising logic circuit means for determining whetheror not the first occurring positive-going edge, and if not to disablethe output of said comparison means.
 6. The invention set forth in claim5 further defined in that said digital counting means includes means forgenerating a disabling signal when the register of said counting meansregisters other than 1 in its hundreds digit, and further means areincluded for applying said register disabling signal to the output ofsaid error detector.